1. Field of the Disclosure
Generally, the present disclosure relates to the fabrication of microstructure devices, such as integrated circuits, and, more particularly, to the formation of dielectric layers of reduced permittivity having etch stop capabilities.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable carriers for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs) and the like. The individual integrated circuits are arranged in an array form, wherein most of the manufacturing steps, which may involve several hundred individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economical constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield. On the other hand, device dimensions are continuously reduced in view of performance criteria, as, typically, reduced transistor dimensions provide increased operating speed.
In modern integrated circuits, the circuit elements are formed in and on a semiconductor layer, while most of the electrical connections are established in one or more “wiring” layers, also referred to as metallization layers, wherein the electrical characteristics, such as resistivity, electromigration, etc., of the metallization layers significantly affect the overall performance of the integrated circuit. Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with a low-k dielectric material, has become a frequently used alternative in the formation of so-called wiring structures comprising metallization layers having metal line layers and intermediate via layers. Metal lines act as intra-layer connections and vias act as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other are necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay may no longer be limited by the circuit elements, for instance by field effect transistors, but may be limited, owing to the increased density of circuit elements, which requires an even more increased number of electrical connections, by the close proximity of the metal lines and vias, since the line-to-line capacitance increases as the spacing decreases. This fact, in combination with a restricted conductivity of the lines due to a reduced cross-sectional area, even though highly conductive metals may be used, results in increased resistance capacitance (RC) time constants. For this reason, traditional dielectrics such as silicon dioxide (k>4) and silicon nitride (k>7) are increasingly replaced in metallization layers by dielectric materials having a lower permittivity, which are therefore also referred to as low-k dielectrics having a relative permittivity of approximately 3 or significantly less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. Additionally, copper may readily diffuse in many low-k dielectrics, while also reactive components, such as oxygen, fluorine and the like, may come into contact with copper due to the limited diffusion blocking capabilities of the low-k dielectric materials.
For this reason, low-k dielectric materials may have to be used in combination with appropriate materials which may provide the desired copper-confining effect and may also be used as efficient etch stop materials during the patterning of the low-k dielectric materials. For example, silicon nitride may be used in combination with low-k dielectric materials, since silicon nitride may act as an efficient diffusion blocking material, for instance, with respect to copper and other reactive components, thereby maintaining integrity of a copper-based metal region. On the other hand, a plurality of plasma-assisted etch processes, as well as wet chemical etch processes, may be available in which silicon nitride exhibits a significantly reduced etch rate compared to other dielectric materials, such as silicon dioxide and a plurality of low-k dielectric materials. In sophisticated semiconductor devices, however, the overall permittivity of the metallization system may be affected by the provision of silicon nitride material, which may have a moderately high dielectric constant of approximately 6 or higher, which may therefore reduce performance gain obtained by the introduction of low-k dielectric materials. For this reason, great efforts have been made in order to develop material compositions that may provide the desired barrier capabilities, while also having a high etch resistance against a plurality of well-established plasma-assisted etch techniques for patterning low-k dielectric materials. One promising candidate in this respect is a nitrogen-containing silicon carbide layer which may be formed on the basis of plasma-assisted chemical vapor deposition (CVD) techniques on the basis of ammonia and trimethyl silane (TMS), which may have a dielectric constant of approximately 5, while at the same time providing the required diffusion blocking capabilities and etch stop qualities. Consequently, significant performance gain may be accomplished in the metallization level of sophisticated semiconductor devices.
The continuing shrinkage of transistor dimensions, however, also involves a plurality of issues at the transistor level that had to be addressed so as to not unduly offset the advantages obtained by steadily decreasing critical dimensions, such as the gate length of MOS transistors. The gate length, that may be highly correlated to the respective channel length, represents a dominant design criterion for enhancing performance of integrated circuits, since, in CMOS technology, transistor characteristics are substantially determined by the electrical behavior of a channel region, which separates drain and source regions and which is controlled on the basis of a gate electrode, which is separated from the channel region by a thin gate dielectric layer. One major problem in scaled transistor structures is to maintain channel controllability, which may be addressed by a plurality of design measures, many of which may be associated with a reduction of charge carrier mobility in the channel region, thereby reducing the overall gain in performance obtained by further reducing device dimensions. It has, therefore, been proposed to improve transistor performance by enhancing the channel conductivity of the transistor elements by increasing charge carrier mobility in the channel region for a given channel length. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which may result in a modified mobility of holes. Thus, performance of P-channel transistors may be efficiently increased by introducing appropriate stress or strain engineering techniques into the fabrication process for sophisticated semiconductor devices. According to one promising approach for creating strain in the channel region of the transistor, the dielectric material that is formed above the basic transistor structure may be provided in a highly stressed state, for instance in a highly compressive state, in order to induce strain at the transistor and in particular in the channel region thereof. For example, the transistor structures are typically enclosed in an interlayer dielectric material, which may provide the desired mechanical and electrical integrity of the individual transistor structures and which may provide a platform for the formation of the additional wiring layers of the metallization system. The interlayer dielectric material may then be appropriately patterned to provide respective openings connected to the contact areas of the transistors, wherein the patterning process, which may represent one of the most critical processes, may be performed on the basis of an etch stop material in combination with the actual interlayer dielectric material.
For example, silicon dioxide is a well-established interlayer dielectric material in combination with silicon nitride, which may act as an efficient etch stop material during the formation of the contact openings. Consequently, the etch stop material, i.e., the silicon nitride material, is in close contact with the basic transistor structure and thus may be efficiently used for inducing strain in the transistors, in particular as silicon nitride may be deposited on the basis of well-established CVD techniques with high internal stress. For instance, silicon nitride may be deposited with high internal compressive stress of up to 2 GPa (Giga Pascal) or higher by selecting appropriate deposition parameters. On the other hand, a moderately high internal tensile stress level may be created up to 1 GPa and higher by appropriately adjusting the process parameters, such as pressure, temperature, gas flow rates and ion bombardment, during the deposition of the silicon nitride material. Consequently, in an attempt to increase the magnitude of strain created in the adjacent channel region, the internal stress level may be increased and the amount of stress material provided around the basic transistor structure may also be increased. It appears, however, that, in sophisticated applications, the dielectric characteristics of the silicon nitride material may reduce overall performance gain, since, in sophisticated device geometries, the stressed silicon nitride material may also be close to metal lines of the very first metallization layer as well as to the gate electrode structures and the contact elements, which may thus result in an increase of the parasitic capacitance, thereby contributing to significant signal propagation delays, as is previously described with reference to the metallization system. For this reason, the thickness of the highly stressed silicon nitride material may be reduced so as to find a compromise between a desired high strain level and an acceptable overall permittivity within the contact level of the semiconductor device under consideration, thereby, however, restricting the degree of performance gain that could be obtained by more fully exploiting the capabilities of stress liner approaches.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.